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| The IR1210 part number has Data Sheet No. PD60165-C been updated and changed to IR4426/IR4427/IR4428 Please see new data sheet IR1210 DUAL LOW SIDE DRIVER Features * Gate drive supply range from 6 to 20V * CMOS Schmitt-triggered inputs with pull-up * Matched propagation delay for both channels * Outputs out of phase with inputs Product Summary IO+/VOUT 1.5A / 1.5A 6V - 20V 85 & 65 ns Description The IR1210 is a low voltage, high speed power MOSFET and IGBT driver. Proprietary latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays between two channels are matched. ton/off (typ.) Package 8 Lead SOIC Block Diagram 1 NC NC 8 INA 2 INA OUTA 7 TO LOAD 3 IR1210 GND Vs INB OUTB 6 INB 4 5 IR1210 ADVANCED INFORMATION Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VS VO VIN PD RthJA TJ TS TL Definition Fixed supply voltage Output voltage Logic input voltage (INA/N & INB/N) Package power dissipation @ TA +25C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) -0.3 Min. -0.3 VS + 0.3 -0.3 -- -- -- -55 -- Max. 25 Units V VS + 0.3 0.625 200 150 150 300 C W C/W Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND. Symbol VS VO VIN TA Definition Fixed supply oltage Output voltage Logic input voltage (INA/N & INB/N) Ambient temperature Min. 6 0 0 -40 Max. 20 VS VS 125 Units V C DC Electrical Characteristics VBIAS (VS) = 15V, TA = 25C unless otherwise specified. The VIN, and IIN parameters are referenced to GND and are applicable to input leads: INA/N and INB/N. The VO and IO parameters are referenced to GND and are applicable to the output leads: OUTA and OUTB. Symbol VIH VIL VOH VOL IIN+ IINIQS IO+ IO- Definition Logic "0" input voltage (OUT=LO) Logic "1" input voltage (OUT=HI) High level output voltage, VBIAS -VO Low level output voltage, VO Logic "1" input bias current (OUT=HI) Logic "0" input bias current (OUT=LO) Quiescent Vs supply current Output high short circuit pulsed current Output low short circuit pulsed current Min. Typ. Max. Units Test Conditions 2.7 -- -- -- -- -- -- 1.5 1.5 -- -- -- -- 5 -10 100 2.3 3.3 -- 0.8 1.2 0.1 15 -30 200 -- A -- A VIN = 0V VIN = VS VIN = 0V or VS VO = 0V, VIN = 0 PW 10 s VO = 15V, VIN = VS PW 10 s V 2 www.irf.com ADVANCED INFORMATION IR1210 Dynamic Electrical Characteristics VBIAS (VS) = 15V, CL = 1000 pF, TA = 25C unless otherwise specified. Symbol td1 td2 tr tf Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Min. Typ. Max. Units Test Conditions -- -- -- -- 85 65 15 10 160 150 35 25 ns figures 2 & 3 Functional Block Diagram 5V Vs INA PREDRV DRV OUTA 5V Vs INB PREDRV DRV OUTB GND Lead Assignment and Definitions Symbol Description VS GND INA INB OUTA OUTB Supply voltage Ground Logic input for gate driver output (OUTA), out of phase Logic input for gate driver output (OUTB), out of phase Gate drive output A Gate drive output B GND INB VS OUTB INA OUTA www.irf.com 3 IR1210 ADVANCED INFORMATION 8 Lead SOIC 01-0021 08 4 www.irf.com ADVANCED INFORMATION IR1210 INA 50% 50% INA INB INB t d1 tr t d2 tf OUTA OUTB OUTA OUTB 90% 10% 90% 10% Figure 1. Timing Diagram Figure 2. Switching Time Waveforms V S = 15V 6 4.7UF 0.1UF INA 2 7 OUTA C L = 1000PF INB 4 5 OUTB C L = 1000PF 3 Figure 3. Switching Time Test Circuit WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/20/2000 www.irf.com 5 |
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